/*****************************************
**                                      **
**             数码管显示模块               **
**                                      **
******************************************/
module display (
    clk_1kHz,
    data_in,
    point_in,
    dm_out,
    wm_out
            );
            
input clk_1kHz;
input [31:0] data_in;        //输入
input [7:0] point_in;        //小数点

output [7:0] dm_out;        //段选信号
output [7:0] wm_out;        //位选信号


reg [2:0] scan_smg;        //数码管扫描寄存器
reg [7:0] dm_out_r;        //段码寄存器
reg [7:0] wm_out_r;        //位码寄存器


//----------------------------------------------------------
always@(posedge clk_1kHz)
begin


  scan_smg<=scan_smg+1\'b1;   
  case(scan_smg)
    3\'b000: begin dm_out_r<=disp(data_in[31:28]) && (point_in[0]?8\'b1111_1111:8\'b0111_1111);  
                  wm_out_r<=8\'b1111_1110;  end
    3\'b001: begin dm_out_r<=disp(data_in[27:24]) && (point_in[1]?8\'b1111_1111:8\'b0111_1111);  
                  wm_out_r<=8\'b1111_1101;  end
    3\'b010: begin dm_out_r<=disp(data_in[23:20]) && (point_in[2]?8\'b1111_1111:8\'b0111_1111);  
                  wm_out_r<=8\'b1111_1011;  end
    3\'b011: begin dm_out_r<=disp(data_in[19:16]) && (point_in[3]?8\'b1111_1111:8\'b0111_1111);  
                  wm_out_r<=8\'b1111_0111;  end
    3\'b100: begin dm_out_r<=disp(data_in[15:12]) && (point_in[4]?8\'b1111_1111:8\'b0111_1111);  
                  wm_out_r<=8\'b1110_1111;  end
    3\'b101: begin dm_out_r<=disp(data_in[11:8])  && (point_in[5]?8\'b1111_1111:8\'b0111_1111);  
                  wm_out_r<=8\'b1101_1111;  end
    3\'b110: begin dm_out_r<=disp(data_in[7:4])   && (point_in[6]?8\'b1111_1111:8\'b0111_1111);  
                  wm_out_r<=8\'b1011_1111;  end
    3\'b111: begin dm_out_r<=disp(data_in[3:0])   && (point_in[7]?8\'b1111_1111:8\'b0111_1111);  
                  wm_out_r<=8\'b0111_1111;  end
    default: ;
  endcase

end
                
//--------------------------------------------------------------                
//数码管译码函数
function[7:0] disp;
input [3:0] a;
 case(a)
  4\'d0:  disp=8\'b1100_0000;
  4\'d1:  disp=8\'b1111_1001;
  4\'d2:  disp=8\'b1010_0100;
  4\'d3:  disp=8\'b1011_0000;
  4\'d4:  disp=8\'b1001_1001; 
  4\'d5:  disp=8\'b1001_0010;
  4\'d6:  disp=8\'b1000_0010; 
  4\'d7:  disp=8\'b1111_1000; 
  4\'d8:  disp=8\'b1000_0000;
  4\'d9:  disp=8\'b1001_0000; 
  default:disp=8\'b1111_1111;
 endcase
endfunction
//--------------------------------------------------------------

assign dm_out=dm_out_r;
assign wm_out=wm_out_r;
endmodule