SystemVerilog Assertions Design Tricks and SVA Bind Files读书笔记
- 1 Introduction
- 1.1 What is an assertion?
- (1)a "statement of fact"or "claim of truth"made about a design
- (2)active design comments
- (3) describing what should never happen using "not sequence" assertions is even more important than using assertions to describe always true conditions.
- 1.2 What is a property?
- (1)a rule that will be asserted (enabled) to passively test a design
- (2)can be a simple Booleantest regarding conditions that should always hold true about the design, or it can be a sampled sequence of signals that should follow a legal and prescribed protocol
- 1.3 Two types of SystemVerilog assertions
- SystemVerilog has two types of assertions:
- (1) Immediate assertions
- (2) Concurrent assertions
版权声明：本文为hxxy原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。