关于自定义IP
1、接口
    a、全局信号 时钟(Clk),复位(reset_n)
    
    b、avalon mm slave  
        地址(as_address)
        片选(as_chipselect /as_chipselect_n)
        写请求(as_write / as_write_n)
        写数据(as_writedata(按照字节对齐,8/16/32位位宽)
        读请求(as_read / as_read_n)
        读数据(as_readdata)(按照字节对齐,8/16/32位位宽)
        
        等待信号(as_waitrequest / as_waitrequest_n)
        读数据有效信号(as_data_valid)
    
        中断请求(irq / irq_n)
    
    c、导出信号,导出到NIOS 系统顶层,分配到IO,或者连接到Qsys系统以外的逻辑

2、内部寄存器和线网的定义
    数据寄存器(读/写)
    状态寄存器(IP运行状态、数据状态……)
    控制寄存器
    中断屏蔽寄存器
    用户自定义寄存器

3、Avalon总线对寄存器的读写

    //写入数据
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        channel <= 3\'d0;
    else if(as_chipselect && as_write && (as_address == 1))
        channel <= as_writedata[2:0];

    //写指定地址实现相应功能,不考虑写入值
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        control <= 1\'d0;
    else if(as_chipselect && as_write && (as_address == 3))
        control <= 1\'d1;
    else
        control <= 1\'d0;
        
    //读寄存器逻辑        
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        as_readdata <= 16\'d0;
    else if(as_chipselect && as_read)begin
        case(as_address)
            0:as_readdata <= {4\'d0, data};
            1:as_readdata <= {13\'d0, channel};
            2:as_readdata <= {8\'d0, freq_sclk};
            4:as_readdata <= {15\'d0, irqmask};
            5:as_readdata <= {14\'d0, status};
            default:as_readdata <= 16\'d0;
        endcase    
    end

4、用户逻辑对寄存器的赋值    
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        status[0] <= 1\'d0;
    else if(Conv_Done)
        status[0] <= 1\'b1;
    else if(as_chipselect && as_read && (as_address == 0))
        status[0] <= 1\'b0;
    
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        status[1] <= 1\'d0;
    else if(ADC_State)
        status[1] <= 1\'b1;
    else 
        status[1] <= 1\'b0;
    

 

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